FOCoS-Bridge with TSV: How ASE's Latest Bridge Die Architecture Cuts Power Loss by 3x for AI and HPC Packaging

AI accelerators and HPC processors now exceed 1,000 W per package. At these power densities, every milliohm of parasitic resistance in the die-to-die interconnect translates directly into wasted energy and excess heat. Standard fan-out bridge architectures route signals laterally through redistribution layers (RDL), but lack a vertical conduction path for power delivery and thermal dissipation — two constraints that tighten simultaneously as chiplet count and high bandwidth memory (HBM) stacks scale upward.

ASE addresses this bottleneck with FOCoS-Bridge with TSV, the newest extension of its VIPack™ FOCoS-Bridge platform. By integrating through silicon vias (TSV) into the bridge die itself, the architecture creates a direct vertical path that reduces resistance by 72% and inductance by 50% compared to the standard FOCoS-Bridge, while simultaneously opening a low-thermal-resistance channel from the active die surface to the package backside.

Test Vehicle Architecture: 14 Dies per Fan-Out Module

The FOCoS-Bridge with TSV test vehicle, presented at the 2025 IEEE 75th Electronic Components and Technology Conference (ECTC), integrates two identical fan-out (FO) modules assembled on a single flip chip ball grid array (FCBGA) substrate in a multi-chip module (MCM) arrangement. Each FO module contains:

  • 1 ASIC die — the primary compute element
  • 4 HBM3 stacks — high bandwidth memory for AI/HPC data throughput
  • 4 TSV-bridge dies — silicon bridge interconnects with integrated through silicon vias
  • 10 IPD (Integrated Passive Device) dies — embedded decoupling capacitors for power delivery optimization

A total of 14 dies are embedded within each FO module. The fan-out module measures approximately 1.8× reticle size (~1,500 mm²), assembled into an 85 mm × 85 mm package body. The TSV-bridge dies and embedded IPD utilize three RDL layers fabricated at 5 μm line width/line spacing (L/S).

FOCoS-Bridge with TSV and IPD test vehicle architecture

FOCoS-Bridge with TSV architecture cross-section showing ASIC, HBM3, TSV-bridge dies, and IPD integration

Why TSV in the Bridge Die Matters

Conventional FOCoS-Bridge technology embeds small silicon pieces with fine-pitch routing layers into the fan-out RDL interposer, connecting chiplets (e.g., GPU to HBM) through lateral interconnects. This architecture delivers die-to-die interconnect density an order of magnitude higher than traditional organic FCBGA — but the lateral-only routing constrains power delivery impedance and thermal dissipation.

Adding TSV to the bridge die introduces three engineering advantages:

Reduced parasitic impedance. The vertical via path shortens the electrical delivery route between the chiplet and the substrate power plane. Measured results show 72% lower resistance and 50% lower inductance versus the standard FOCoS-Bridge, directly improving power integrity for high-current AI accelerators.

Enhanced thermal dissipation. TSVs act as thermal conduits, creating a low-resistance heat path from the bridge die surface through the silicon to the package backside. For HPC processors operating above 500 W, this additional thermal channel reduces junction-to-case thermal resistance without requiring changes to the heat sink or cooling solution.

Embedded passive integration. The IPD dies co-embedded alongside TSV-bridge dies enable on-package decoupling capacitors, reducing power delivery network (PDN) impedance at high frequencies. This is critical for chiplet architectures where voltage droop during transient load switching can degrade signal integrity across the die-to-die interface.

Assembly Process: Thermocompression Bonding Enables Large-Module Integration

Assembling a fan-out module exceeding 1,500 mm² with 14 embedded dies presents significant warpage challenges. The coefficient of thermal expansion (CTE) mismatch among silicon dies, RDL layers, molding compound, copper pillars, bridge dies, microbumps, and the organic substrate creates complex stress distributions during reflow.

ASE's research compared two assembly techniques for chip-on-substrate (CoS) integration:

Parameter Mass Reflow (MR) Thermocompression Bonding (TCB)
Warpage control Limited at large module sizes Superior — enables >1.8× reticle modules
Solder joint quality Inconsistent for fine-pitch Reliable fine-pitch interconnects
Process compatibility with TSV-bridge Partial Full — validated for TSV + IPD integration
Alignment accuracy Standard High — required for microbump pitch

The results demonstrated that thermocompression bonding (TCB) effectively enables the successful integration of FOCoS-Bridge with TSV and embedded IPD, achieving the solder joint integrity and alignment accuracy required for high-density chiplet packaging. This finding builds on ASE's prior TCB development for FOCoS-Bridge, where test vehicles with 10 chiplets and 10 silicon bridge dies (>3× reticle size) passed reliability tests with no delamination or cracking at any interface.

Mass Reflow vs Thermocompression Bonding assembly comparison for FOCoS-Bridge with TSV

FOCoS-Bridge with TSV within the VIPack™ Platform

FOCoS-Bridge with TSV extends ASE's VIPack™ advanced packaging platform, which provides six technology pillars for heterogeneous integration: FOCoS, FOCoS-Bridge, FOPoP, FOSiP, 2.5D IC, and 3D IC. Within this platform, FOCoS-Bridge with TSV specifically targets applications requiring:

  • Multi-die + HBM integration for AI training accelerators and data center GPUs where bandwidth exceeds 4 TB/s per package
  • Power-sensitive chiplet architectures where parasitic losses in the bridge interconnect directly impact energy efficiency (performance per watt)
  • High-thermal-density processors for HPC and machine learning inference where junction temperatures must remain below specification without exotic cooling

Compared to 2.5D silicon interposer solutions, FOCoS-Bridge with TSV retains the cost and scalability advantages of fan-out packaging — no full-size interposer is required, silicon is used only where chiplet-to-chiplet connections occur — while closing the electrical and thermal performance gap through vertical TSV integration.

ASE's Integrated Design Ecosystem™ (IDE 2.0) supports co-design across silicon, package, and system domains for FOCoS-Bridge with TSV implementations, enabling signal integrity, thermal, and power delivery co-optimization before tape-out.

Applications: AI, HPC, and Data Center Infrastructure

FOCoS-Bridge with TSV addresses the packaging requirements of next-generation compute platforms:

AI training and inference. Large language model (LLM) training clusters require GPU packages with maximum memory bandwidth and minimum power loss in the die-to-die interconnect. The 72% resistance reduction directly translates to lower I²R losses at the 100+ ampere currents typical of modern AI accelerators.

High-performance computing. Scientific simulation and weather modeling workloads demand sustained compute throughput with predictable thermal behavior. The enhanced thermal path through TSV-bridge dies supports stable operation at sustained high power without throttling.

Data center networking. Co-packaged optics (CPO) and high-radix switch ASICs require low-inductance power delivery to maintain signal integrity at 112 Gbps PAM4 serdes rates. The 50% inductance reduction in FOCoS-Bridge with TSV supports cleaner power delivery at these frequencies.

Conference Publication

This work was published at the 2025 IEEE 75th Electronic Components and Technology Conference (ECTC) in Dallas, Texas (May 27–30, 2025). Full citation: T. C. Lee, C. H. Chen, L. Cao, Y. S. Su, C. J. Zhuang, and H.-C. Kuo, "Technology Enhancements on FOCoS-Bridge for Emerging Trends in HPC and AI," 2025 IEEE 75th ECTC. DOI: 10.1109/ECTC51687.2025.00158

Explore ASE's advanced packaging solutions for your next AI or HPC design at ase.aseglobal.com.

Frequently Asked Questions

Q: What is FOCoS-Bridge with TSV and how does it differ from standard FOCoS-Bridge? A: FOCoS-Bridge with TSV integrates through silicon vias (TSV) directly into the silicon bridge die that connects chiplets within ASE's fan-out packaging platform. Standard FOCoS-Bridge routes signals laterally through RDL layers only. Adding TSV creates a vertical electrical and thermal path, reducing resistance by 72% and inductance by 50% while improving heat dissipation from bridge die to package backside.

Q: Why is thermocompression bonding (TCB) required for advanced fan-out packaging? A: Large fan-out modules exceeding 1,500 mm² with multiple embedded dies experience significant warpage from CTE mismatch between silicon, RDL, and molding materials. Thermocompression bonding provides the controlled alignment accuracy and thermal profile needed to achieve reliable fine-pitch solder joints, which standard mass reflow cannot consistently deliver at these module sizes.

Q: How does FOCoS-Bridge compare to 2.5D silicon interposer packaging? A: Both technologies provide fine-pitch die-to-die interconnect for chiplet integration. FOCoS-Bridge embeds small silicon bridge pieces only where chiplet connections are needed, rather than using a full-size silicon interposer spanning the entire package. This reduces silicon consumption and cost while eliminating the reticle size constraint of interposers. FOCoS-Bridge with TSV closes the electrical and thermal gap with 2.5D by adding vertical via paths through the bridge die.

Q: What role does VIPack™ play in ASE's advanced packaging portfolio? A: VIPack™ is ASE's vertically integrated advanced packaging platform comprising six technology pillars: FOCoS, FOCoS-Bridge, FOPoP, FOSiP, 2.5D IC, and 3D IC. Each pillar addresses specific heterogeneous integration requirements — from ultra-high-density RDL fan-out to TSV-based 3D stacking. The platform is supported by ASE's Integrated Design Ecosystem™ (IDE 2.0) for co-design across silicon, package, and system domains.

Q: What applications benefit most from FOCoS-Bridge with TSV technology? A: FOCoS-Bridge with TSV is designed for compute-intensive applications requiring high memory bandwidth and low-loss power delivery: AI training accelerators with HBM integration, HPC processors for scientific simulation, and data center networking ASICs requiring co-packaged optics. The 72% resistance reduction is particularly valuable for AI accelerators operating at 100+ ampere currents, where parasitic I²R losses in the die-to-die interconnect directly impact energy efficiency.

About ASE, Inc.

Advanced Semiconductor Engineering, Inc. (ASE) is a member of ASE Technology Holding Co., Ltd. (NYSE: ASX, TAIEX: 3711), the world's leading provider of semiconductor packaging and testing services. ASE develops and offers a wide range of advanced semiconductor packaging and testing solutions and services, including system-in-package (SiP), 2.5D & 3D IC packaging, fan-out packaging, and related services. More information about ASE is available at ase.aseglobal.com.

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原始文章 Original →: Technology Enhancements on FOCoS-Bridge for Emerging Trends in HPC and AI