Premiering ASE Technology and Solutions at 2021 WSCE China
When ASE, Siliconware Precision Industries Co., Ltd. (SPIL) and Universal Scientific Industrial Co., Ltd. (USI) walked into the 2021 World Semiconductor Conference in Nanjing together, the message was structural. Three operating companies of the same group — packaging, advanced packaging, and module manufacturing — showed up as a single solution platform spanning System-in-Package (SiP), advanced packaging, and Heterogeneous Integration (HI). For a chip designer in the 5G+AI era, that combination is the practical answer to a problem Moore's Law alone no longer solves: how to deliver higher performance, smaller size and lower power, all at once.
A Single Platform Built from Three Companies
A platform is only useful if it covers what a customer actually needs end-to-end, and the WSCE showcase was organized around that test. ASE provides the broad packaging and test foundation. SPIL contributes a deep advanced-packaging and chiplet-packaging portfolio. USI delivers miniaturized wireless and module solutions for the device side. The synergy between the three is what lets the group act as a primary architect in Heterogeneous Integration, where separately manufactured dies, memory, surface mount devices, sensors and pre-assembled subsystems are brought into one package or module.
Heterogeneous Integration matters because it sidesteps the cost and complexity of pushing every function into a single monolithic system-on-chip. By letting each die be designed and manufactured in the process technology that suits it best, then combining them through advanced packaging, the group helps customers attack high-performance computing (HPC), Internet of Things (IoT) and automotive electronics without forcing every chip onto the same node.
The Synergy of ASE, SPIL and USI
The technical scope on display at WSCE China lined up across four directions, each anchored in real product technology rather than slideware.
| Capability | Owner | What it enables |
|---|---|---|
| Chip-First and Chip-Last Fan-Out packaging | ASE | High-density, high-performance computing chip designs |
| 2.5D/3D IC packaging | ASE | High bandwidth, low latency for compute and memory |
| Chiplet packaging portfolio: FO-MCM+EHS-FCBGA, HBW-POP, FO-POP, ETS-SiP, FO-SD | SPIL | Production-grade chiplet integration options |
| Miniaturized wireless and module SiP: LTE Cat.1, TWS Bluetooth, dual-core MCU with Bluetooth 5/OpenThread/ZigBee 3.0 | USI | Small-footprint connected devices |
Two points are worth pulling out. First, Fan-Out is offered in both Chip-First and Chip-Last variants — the same option that lets ASE tune redistribution layer (RDL) yield risk and substrate cost against a given customer's design. Second, SPIL's chiplet portfolio is described as design and manufacturing experience, not a roadmap: FO-MCM+EHS-FCBGA (Fan-Out Multi-Chip-Module + Exposed Heat Sink-Flip Chip BGA), HBW-POP (High Bandwidth Package-on-Package), FO-POP (Fan-Out Package-on-Package), ETS-SiP (Embedded Trace Substrate-System in Package) and FO-SD (Fan Out-Single Die) are options a customer can pick from, not concepts. On the USI side, the focus is the opposite end of the integration spectrum — fitness watches, wearables, TWS headsets, mobile devices, routers, industrial IoT, healthcare and tracking devices — where module-level SiP is the difference between a product that ships and a board that fits.
Enabling a Smarter World: Where the Platform Lands
The same technology stack lands across the application markets that drive most of the group's revenue. For smart factories, smart cities and IoT, ASE and SPIL provide complete packaging solutions and USI supplies the System-on-Modules that go into deployed equipment. In smart automotive, the portfolio spans wire bond, flip chip, wafer-level chip-scale package (WLCSP), SiP and discrete packaging on the ASE/SPIL side, with USI's automotive power control modules on the system side. ISE Labs China — the group's first engineering center in China — adds the automotive electronics qualification that turns those packages into shipping product, with VDA6.3 and AECQ certification and mass production qualifications for automotive electronic chips.
In smart wearables, the same compression problem plays out at module scale. ASE's TWS SiP modules pack more functions onto the limited area of a true wireless stereo earbud, and DockSiP and MicroSiP packaging solutions support miniaturization and ease of integration. The portfolio extends into integrated MEMS and sensors, low-power antenna packaging and double-sided thin wireless communications — the building blocks for products whose constraints are millimeters and milliwatts.
What the WSCE Talk Said About the Industry
Invited to speak at the conference's Innovation Summit, Dr. KK Kuo, VP, R&D at ASE China, framed the moment plainly: "The 5G+AI digital era and the evolution of Moore's Law has accelerated the demand for chip miniaturization, high performance and low power consuming chips that contribute to continuous breakthroughs in advanced packaging technology. Heterogeneous integration applications are on track to demonstrate explosive growth in the future, driven by rapid growth in high-performance computing (HPC), 5G, application processor engines (APC), automotive radars, radio frequency, audio, power management integrated circuits (PMIC) and many other applications. High-density packaging will increase in importance and advanced packaging and SiP will help drive the development for the next generation of semiconductor technologies. ASE Group will continue to play a leading role through innovation, prudent investments and industry collaboration."
The substance underneath that statement is that advanced packaging and SiP are not adjacent to the compute roadmap; they are part of it. As transistor scaling slows, packaging is where the next generation of cost-performance gains is being unlocked — and the WSCE platform is the form that work takes inside the ASE group.
What This Means for a Customer Evaluating the Group
For a chip designer or system integrator deciding where to land a complex product, the WSCE showcase is a useful map. A chiplet-based HPC accelerator can use SPIL's chiplet packaging portfolio or ASE's Fan-Out and 2.5D/3D IC options. A 5G or IoT module that needs tight area and power can sit inside USI's wireless SiP work. An automotive part needing AEC qualification can move through ISE Labs China without restarting at a third party. The same group covers all three paths.
That is the value of presenting the three operating companies as one platform: a customer does not have to assemble the supply chain themselves. From package design through chiplet integration, module assembly, automotive qualification and test, the group can keep a complex program inside one organization — and the same engineering teams that develop a new package technology are the ones that take it to volume production.
What Comes Next
The roadmap Dr. Kuo described — explosive growth in heterogeneous integration applications across HPC, 5G, automotive radar, RF, audio and PMIC — is the same roadmap the rest of ASE's portfolio has continued to execute against in the years since 2021. The WSCE platform marked an early articulation of that strategy: not a single product launch, but a public statement that ASE, SPIL and USI together intend to be the place where heterogeneous integration is engineered, productized and shipped.
Evaluating advanced packaging, chiplet integration or SiP for your next product? Explore the full ASE, SPIL and USI portfolio at ase.aseglobal.com.
Frequently Asked Questions
Q: What did ASE, SPIL and USI showcase at the 2021 WSCE in Nanjing? A: The three operating companies of the ASE group presented a single solution platform spanning System-in-Package (SiP), advanced packaging and Heterogeneous Integration (HI). It covered Chip-First and Chip-Last Fan-Out packaging, 2.5D/3D IC, SPIL's chiplet packaging portfolio (FO-MCM+EHS-FCBGA, HBW-POP, FO-POP, ETS-SiP, FO-SD) and USI's miniaturized wireless and module SiP solutions.
Q: Why is heterogeneous integration important in the 5G+AI era? A: As Moore's Law slows, integrating every function on a single monolithic system-on-chip becomes increasingly costly and complex. Heterogeneous integration uses advanced packaging to combine separately manufactured dies, memory, passive components and sensors into one package — each made in the process technology that suits it best — which is how the industry continues to deliver higher performance, smaller size and lower power for HPC, 5G, automotive and IoT.
Q: What chiplet packaging options does SPIL provide? A: SPIL's chiplet packaging portfolio at WSCE 2021 included FO-MCM+EHS-FCBGA (Fan-Out Multi-Chip-Module with Exposed Heat Sink Flip Chip BGA), HBW-POP (High Bandwidth Package-on-Package), FO-POP (Fan-Out Package-on-Package), ETS-SiP (Embedded Trace Substrate System-in-Package) and FO-SD (Fan-Out Single Die). These are production options, not concepts.
Q: How does USI fit into the ASE group's offering? A: USI focuses on miniaturized wireless and module SiP solutions — LTE Cat.1 communication modules, TWS Bluetooth audio modules, wireless communication modules and dual-core wireless MCUs with Bluetooth 5, OpenThread and ZigBee 3.0 — used in fitness watches, wearables, TWS headsets, mobile devices, routers, industrial IoT, healthcare devices and tracking devices. Where ASE and SPIL handle package and chip integration, USI handles module-level integration into shipping products.
Q: What role does ISE Labs China play in the automotive portfolio? A: ISE Labs China is the group's first engineering center in China to hold VDA6.3 and AECQ certification and mass production qualifications for automotive electronic chips. Together with ASE and SPIL's wire bond, flip chip, WLCSP, SiP and discrete packaging and USI's automotive power control modules, it lets an automotive customer move a part from package development through qualification to volume production inside one organization.
✏️ AI 標題改寫建議
原始標題： Premiering ASE Technology and Solutions at 2021 WSCE China
建議標題： ASE, SPIL and USI at WSCE 2021: One Heterogeneous Integration Platform for the 5G + AI Era
改寫理由： 原標題僅交代「在 WSCE 首秀」這個動作，缺少技術主軸與讀者價值。建議標題把三家營運公司具名列出，點出「Heterogeneous Integration platform」的核心定位，並以「5G + AI Era」帶出當下產業驅動力與 SEO 關鍵字（WSCE 2021、HI、SPIL、USI），讓讀者一眼看到「這篇文章談什麼、為何要看」。依 skill 規則，Ghost 文章標題沿用原始標題，本建議僅供編輯團隊參考。
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原始文章 Original → Premiering ASE Technology and Solutions at 2021 WSCE China
