Siemens and ASE Introduce Enablement Technologies for Next-Generation High Density Advanced Package Designs

Designing a 2.5D or 3D IC package has historically meant iterating blindly: package architects plan assembly and interconnect scenarios, hand them off, and wait through long verification cycles before learning whether a layout will actually close. Advanced Semiconductor Engineering, Inc. (ASE) and Siemens Digital Industries Software have set out to compress that loop, introducing two enablement solutions that cut 2.5D/3D IC and Fan-Out Chip-on-Substrate (FOCoS) package assembly planning and verification cycle times by roughly 30 to 50 percent per design iteration.

The two solutions let mutual customers create and evaluate multiple complex integrated circuit (IC) package assemblies and interconnect scenarios in a single, data-robust graphical environment — before and during physical design implementation, rather than after. They stem from ASE's participation in the Siemens OSAT Alliance, a program built to accelerate adoption of high-density advanced packaging (HDAP) technologies including 2.5D, 3D IC, and Fan-Out wafer-level packaging (FOWLP).

A 30–50% Cut in Assembly Planning and Verification Cycles

The headline result is the time saved. By adopting Siemens' Xpedition Substrate Integrator software and Calibre 3DSTACK platform, and integrating them with ASE's existing design flow, the partners reduced 2.5D/3D IC and FOCoS package assembly planning and verification cycle times by about 30 to 50 percent in each design iteration. Because advanced packages typically require many iterations to converge, a per-iteration saving of that magnitude compounds across a full project, pulling in the schedule for getting a multi-die package to production.

Just as important, the flow lets ASE and its customers close physical verification issues for the entire wafer package assembly earlier in the cycle. Catching interconnect and assembly problems during planning — instead of after a costly verification pass — is where the time savings actually originate.

The Assembly Design Kit (ADK) for FOCoS and 2.5D MEOL

At the center of the collaboration is an assembly design kit (ADK) that lets customers using ASE's Fan-Out Chip-on-Substrate (FOCoS) and 2.5D Middle End of Line (MEOL) technologies fully leverage the Siemens HDAP design flow. FOCoS is one of the core technologies in ASE's VIPack™ advanced packaging platform, using redistribution layer (RDL) interconnects to integrate multiple dies on a fan-out substrate — and an ADK gives designers a validated, ready-to-use bridge between that packaging technology and the EDA environment they design in.

A fully validated ADK matters because it removes guesswork. Instead of manually translating ASE's process rules into the design tool, customers inherit a qualified kit, which is what enables the friction-free transition from classic chip designs toward 2.5D, 3D IC, and Fan-Out solutions.

Why the OSAT Alliance Model Works

The OSAT Alliance program promotes the adoption, implementation, and growth of HDAP across the semiconductor ecosystem and design chain. Its purpose is to give system and fabless semiconductor companies a friction-free path to emerging packaging technologies — letting mutual customers fully leverage the Siemens HDAP flow and bring innovations to market quickly for internet of things (IoT), automotive, 5G network, artificial intelligence (AI), and other fast-growing IC applications.

The alliance also commits ASE and Siemens to extend their partnership toward a single design platform spanning FOWLP through 2.5D substrate design. A unified platform across packaging types reduces the tool fragmentation that slows multi-technology programs, which matters as designs increasingly mix fan-out, 2.5D, and 3D approaches in one product.

"By adopting the Siemens Xpedition Substrate Integrator and Calibre 3DSTACK technologies, and through integration with the current ASE design flow, we can now leverage this mutually developed flow to significantly reduce 2.5D/3D IC and FOCoS package assembly planning and verification cycle times by about 30 to 50 percent in each design iteration," said Dr. C.P. Hung, Vice President, ASE Group. "Through the comprehensive design flow, we can now more quickly and easily co-design with our customers for 2.5D/3D IC and FOCoS design, and close any physical verification issues for their entire wafer package assembly."

"We are pleased that ASE continues to develop highly innovative IC packaging solutions as part of our OSAT Alliance," said AJ Incorvaia, Senior Vice President and General Manager, Electronic Board Systems Division, Siemens Digital Industries Software. "By providing a fully validated ADK for ASE's leading-edge FOCoS and 2.5D MEOL technologies, we expect to enable customers to more easily transition from classic chip designs to 2.5D, 3D IC, and Fan-Out solutions."

Design Enablement as a Competitive Advantage

For ASE, design enablement is inseparable from packaging capability. A 2μm/2μm FOCoS interconnect is only valuable to a customer who can design to it confidently and verify it quickly. By co-developing a qualified flow with Siemens and packaging it as an ADK, ASE turns its HDAP process expertise into something customers can act on inside their own EDA tools — shortening the path from concept to a manufacturable 2.5D, 3D IC, or Fan-Out package, and reinforcing ASE's role as a turnkey partner from design collaboration through volume production.

Designing a 2.5D, 3D IC, or Fan-Out package? Explore ASE's advanced packaging and design enablement capabilities at ase.aseglobal.com.

Frequently Asked Questions

Q: What is high-density advanced packaging (HDAP)? A: HDAP refers to advanced packaging technologies that integrate multiple dies at high interconnect density, including 2.5D, 3D IC, and Fan-Out wafer-level packaging (FOWLP). These approaches enable heterogeneous integration for IoT, automotive, 5G, and AI applications where conventional single-die packaging falls short.

Q: What is the Siemens OSAT Alliance? A: The Siemens OSAT Alliance is a program designed to accelerate adoption of HDAP technologies across the semiconductor ecosystem. Through it, ASE and Siemens co-developed enablement solutions that give system and fabless companies a friction-free path from classic chip design to 2.5D, 3D IC, and Fan-Out solutions.

Q: What is an assembly design kit (ADK)? A: An ADK is a validated kit that lets designers use a foundry or OSAT's packaging technology directly within their EDA flow. ASE's ADK supports its Fan-Out Chip-on-Substrate (FOCoS) and 2.5D Middle End of Line (MEOL) technologies within the Siemens HDAP design flow, removing manual rule translation.

Q: How much do the Siemens-ASE enablement solutions speed up design? A: By integrating Siemens' Xpedition Substrate Integrator and Calibre 3DSTACK with ASE's design flow, the partners reduced 2.5D/3D IC and FOCoS package assembly planning and verification cycle times by about 30 to 50 percent per design iteration.

Q: What is FOCoS and how does it relate to ASE's VIPack™ platform? A: Fan-Out Chip-on-Substrate (FOCoS) integrates multiple dies on a fan-out substrate using redistribution layer (RDL) interconnects. It is one of the core technologies in ASE's VIPack™ advanced packaging platform, used for chiplet integration in high-performance applications.

✏️ AI 標題改寫建議

原始標題： Siemens and ASE introduce enablement technologies for next-generation high density advanced package designs

建議標題： ASE and Siemens Cut 2.5D/3D IC and FOCoS Design Cycles by Up to 50% with a Validated HDAP Flow

改寫理由： 原始標題冗長且無量化利益。建議標題以最具差異化的數據（縮短 30–50% 設計週期）開場，符合 Rule 1（量化）與 Rule 7（讀者利益），並保留 2.5D/3D IC、FOCoS、HDAP 關鍵字，精準鎖定封裝設計工程師讀者。

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