Advanced Packaging Evolution: Chiplet and Silicon Photonics-CPO

Reaching ExaFLOPS-class AI compute requires interconnecting at least 1,000 AI chiplets through high-density redistribution layer (RDL) routing — and the AI clusters beyond that will link millions of chiplets. As Moore's Law slows, data-rate demands are surpassing what any single semiconductor technology can deliver, which makes heterogeneous integration (HI) the practical route past the bandwidth bottleneck. That route now runs through two parallel tracks: denser electrical chiplet integration, and the shift to optical interconnect through Co-Packaged Optics (CPO).

The first evolution in AI hardware is using advanced HI packaging to integrate chiplets from diverse wafer nodes — particularly logic and memory. ASE offers a spectrum of high-density solutions, and the design decision is matching routing density to each link rather than over-building everywhere:

  • 2.5D IC places chiplets on a redistribution layer (RDL) over a silicon interposer, reaching line width/line spacing (L/S) down to 0.5μm/0.5μm — the highest density, ideal for the most demanding logic-to-memory links.
  • FOCoS (Fan-Out Chip-on-Substrate) uses fan-out RDL to integrate chiplets at an L/S ranging from 2μm/2μm to 10μm/10μm — a cost-effective alternative where interposer-grade routing isn't required.
  • FOCoS-Bridge embeds silicon bridges for high-density routing only in the zones demanding high-speed transmission, fanning out the rest — offering both 0.5μm/0.5μm and 2μm/2μm in a single package.

The payoff is system-level. By raising I/O density and shrinking the interconnection distance across the roughly 10 chiplets in a typical AI package, these solutions can reduce system size by up to 70% and improve computing performance by up to 10x. In the long run, the ideal endpoint is treating a full-scale wafer as a single packaged device — the only way to interconnect the 1,000-plus chiplets an ExaFLOPS machine needs.

Why the Industry Is Turning to Optics

Electrical interconnect has a ceiling. As chiplet counts climb toward the millions, the transmission losses of copper become the limiting factor, while optical interconnect offers significantly lower loss over distance. That physics is why photonic integration has moved from research curiosity to roadmap priority, and why major international programs — photonixFAB in Europe, DARPA initiatives in the U.S., and the IOWN global forum in Japan — converge on the same approach: Co-Packaged Optics (CPO).

CPO brings the optics into the package itself. In a typical networking configuration, a switch ASIC sits at the center, surrounded by multiple photonic engines (optical engines, or OEs). Assembling one is genuinely complex: it combines lasers, optics, fiber array units (FAUs), and silicon ICs spanning several wafer nodes — photonic integrated circuits (PICs), electronic integrated circuits (EICs), and memory ICs. Some designs add specialized post-CMOS wafer processes such as deep reactive ion etching (DRIE) cavity formation, AuSn bonding, KOH V-grooves, or fan-out RDL. Integrating all of it into one package, then testing it, is among the hardest assembly flows in the industry — and the two processes that decide its success are EIC/PIC 3D integration and fiber assembly.

EIC/PIC 3D Integration: Two Routes to Vertical Stacking

To minimize the distance between the electronic and photonic dies, ASE stacks them vertically using chip-on-wafer 3D integration — shrinking form factor while improving both bandwidth density and energy efficiency. Two approaches handle the vertical interconnect.

In Option 1 (PIC on top of EIC), forming through silicon via (TSV) structures in the EIC is difficult because the EIC is usually built on an advanced node. ASE instead uses a wafer-level fan-out process to form tall copper pillars for the vertical link to the top PIC. The resulting Photonic FOPoP (Fan-Out Package-on-Package) excels at optical coupling, because the overhanging portion of the PIC enables optical edge coupling.

In Option 2 (PIC on the bottom), TSVs formed in the PIC carry the vertical interconnect to the top EIC. Here, FAU assembly and PIC warpage control are critical. This Photonic Non-mold 3D structure delivers better thermal dissipation and a higher transmission data rate — over 200G per lane — thanks to cleaner power and signal integrity. For silicon photonics at these data rates, PIC with TSV becomes indispensable.

Fiber-to-PIC Assembly: Performance vs. Manufacturability

Coupling fiber to the PIC forces a trade-off between optical performance and high-volume manufacturability. For the best optical result — minimizing optical loss and wavelength sensitivity — edge coupling with active alignment using lenses is the superior choice. But active alignment is slow, and high-volume manufacturing needs wafer-scale optical testability. That pushes production toward a chip-on-wafer mirror coupler using passive alignment.

The industry is therefore shifting to wafer-scale assembly using vertical couplers for optical and FAU assembly in high-volume CPO. These couplers expand the laser beam size for greater coupling tolerance, allow wafer-scale testing, support detachable FAUs, and are less sensitive to wavelength variation — which is what makes them compatible with Dense Wavelength Division Multiplexing (DWDM) systems.

Building a Synergistic Ecosystem

No single company spans lasers, PICs, EICs, foundry nodes, and assembly. Realizing CPO at volume depends on a synergistic ecosystem among system integrators, design houses, foundries, and outsourced semiconductor assembly and test (OSAT) providers — and on defining specifications clearly enough to develop known-good optical engine (OE) solutions that streamline the supply chain. As the world's largest OSAT, ASE is positioned at the assembly center of that ecosystem, contributing both the electrical chiplet platforms and the silicon photonics packaging that AI's next decade will run on.

Conclusion

The evolution of AI packaging is two-track: match electrical interconnect density to the link — 0.5μm/0.5μm on a silicon interposer, 2μm/2μm to 10μm/10μm with FOCoS, both in FOCoS-Bridge — to cut system size up to 70% and lift performance up to 10x today; and adopt CPO with EIC/PIC 3D integration and wafer-scale fiber assembly to break the electrical bandwidth ceiling tomorrow. ASE's Silicon Photonics packaging platform and VIPack™ portfolio give system architects both tracks from one partner, spanning design, packaging, and test.

Explore chiplet and CPO packaging: See how ASE's Silicon Photonics platform and VIPack™ portfolio can scale your AI system at ase.aseglobal.com.

Frequently Asked Questions

Q: What is Co-Packaged Optics (CPO)? A: CPO integrates optical engines into the same package as a switch ASIC, replacing long electrical links with optics to cut transmission loss. A typical configuration places the switch ASIC centrally, surrounded by photonic engines built from lasers, optics, fiber array units (FAUs), and silicon ICs including PICs, EICs, and memory.

Q: How do FOCoS, FOCoS-Bridge, and 2.5D differ in interconnect density? A: 2.5D on a silicon interposer reaches L/S of 0.5μm/0.5μm, FOCoS fan-out RDL ranges from 2μm/2μm to 10μm/10μm, and FOCoS-Bridge combines both 0.5μm/0.5μm and 2μm/2μm by embedding silicon bridges only where high-speed routing is needed.

Q: How much can advanced chiplet packaging improve an AI system? A: By raising I/O density and shrinking the interconnection distance across the roughly 10 chiplets in a typical AI package, ASE's high-density solutions can reduce system size by up to 70% and improve computing performance by up to 10x.

Q: What are the two main approaches to EIC/PIC 3D integration? A: Option 1 places the PIC on top of the EIC and uses wafer-level fan-out tall copper pillars (Photonic FOPoP) for good optical edge coupling. Option 2 places the PIC on the bottom with TSVs for vertical interconnect (Photonic Non-mold 3D structure), giving better thermal dissipation and over 200G per lane.

Q: Why is the industry moving to wafer-scale fiber assembly for CPO? A: Edge coupling with active alignment gives the best optical performance but is too slow for volume. Wafer-scale assembly with vertical/mirror couplers using passive alignment enables wafer-scale testing, detachable FAUs, greater coupling tolerance, and DWDM compatibility — making high-volume CPO manufacturing practical.

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原始標題： Advanced Packaging Evolution: Chiplet and Silicon Photonics-CPO

建議標題： From 0.5μm Chiplets to Co-Packaged Optics: The Two-Track Roadmap to ExaFLOPS AI Packaging

改寫理由： 原始標題點出主題但缺乏量化與利益訴求。建議標題以「兩條軌道」框架與可量化端點（0.5μm、ExaFLOPS）凸顯文章結構與規模感，更吸引資料中心與 AI 硬體決策者。依 skill 規則，Ghost 文章標題沿用原始標題。

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原始文章 Original → Advanced Packaging Evolution: Chiplet and Silicon Photonics-CPO