Advanced Packaging from FOWLP to FOPLP Development of FanOut Chip Last in 300 mm Panel

A 300mm wafer can hold only nine interposers at 5.5x reticle size — roughly 60mm × 70mm each. A 300mm square panel fits sixteen of the same interposers. That single ratio, a 1.78x gain in usable area, is why ASE moved its fan-out chip-last development from the round wafer to the square panel. In a 2025 ECTC paper, an ASE team led by Teck Chong Lee demonstrated Fan-Out Chip Last technology built on a 300mm panel platform, integrating ten chiplets with ten silicon bridge dies and passing reliability testing with no delamination across any interlayer.

For high-performance computing (HPC) and artificial intelligence (AI) accelerators, that result matters because the package, not the transistor, has become the bottleneck for scaling compute.

Why Fan-Out Outgrew the Wafer

Advanced AI and HPC architectures place high bandwidth memory (HBM) stacks side by side with GPU or ASIC compute dies on a shared interposer, rather than spreading them across a printed circuit board. Shortening the distance between memory and logic raises bandwidth and capacity — but it forces interposers to keep growing as more chiplets crowd onto a single substrate. ASE has already qualified interposers at three times reticle size, with customer roadmaps trending toward 3.5x, 4.5x, and 5.5x.

Wafer-level fan-out packaging (FOWLP) is the incumbent, but it strains at these dimensions. Circular substrates waste area at the edge as die sizes grow, warpage becomes harder to control, and carrier utilization drops. Panel-level fan-out packaging (FOPLP) answers each of those limits: a rectangular panel uses its area more completely, improves material efficiency, and reduces handling and transfer time, which raises throughput and lowers cost per package. For interposers larger than 3x reticle size, the panel process clearly outperforms the wafer.

What the Paper Built: Chip-Last on a 300mm Panel

The two main fan-out chip-on-substrate routes are Chip First and Chip Last. Chip First places dies on a carrier, molds them, then forms the redistribution layer (RDL) on top — practical for two or three small dies on a sub-1x reticle interposer. Chip Last inverts the order: the RDL interposer is built first, then known-good dies are attached to it. Because the RDL is completed before any expensive die is committed, Chip Last is the route the industry uses to integrate large ASICs with HBM, where interposers exceed 1x reticle and may eventually require up to nine RDL layers, including at least seven fine-line layers at line width/line spacing (L/S) of 2μm/2μm.

ASE's paper carried that Chip Last flow onto the panel with two test vehicles:

Test vehicle	Construction	Reliability outcome
TV-1	FOPLP integrating 10 chiplets (SoC-1 + SoC-2) with 10 Si bridge dies	Excellent adhesion, no delamination across all interlayers
TV-2	FOPLP integrating SoC-1 + SoC-2 dies with multiple-layer RDL	Passed reliability tests, confirmed exceptional interlayer quality

The silicon-bridge construction in TV-1 mirrors ASE's FOCoS-Bridge architecture, where a silicon bridge die supplies ultra-fine routing (L/S below 0.5μm/0.5μm) for die-to-die links, while the surrounding panel RDL handles wider-pitch power and signal delivery at around 5μm/5μm. Splitting the routing this way lets the panel-level RDL stay manufacturable while the bridge carries the dense interconnect.

The Process Problem: Round Recipes Don't Run on Squares

Moving from a circular wafer to a square panel breaks several process assumptions, and the paper is candid about the engineering that closed the gap. Spin coating, the standard way to deposit photoresist on a wafer, cannot coat a panel uniformly; ASE switched to slit coating and reformulated the materials to match. Lithography changed too. An interposer for AI chiplet integration is typically larger than a single exposure field, which on a wafer scanner demands multi-reticle stitching. ASE adopted Laser Direct Imaging (LDI), a maskless technique that patterns the full panel without stitching and compensates for panel distortion through software rather than hardware.

On top of patterning, the team specifically investigated panel warpage, chip-on-panel solder joint integrity, and process optimization — the three failure modes that decide whether a large panel survives assembly. Controlling slit-coating uniformity, lithography accuracy, and electroplating thickness across a 300mm square are the practical levers, and clearing them is what let both test vehicles pass stress testing intact.

Where This Fits in ASE's VIPack™ Roadmap

This work is one rung on a longer ladder. ASE is developing an automated FOPLP production line on a 310mm × 310mm panel, with a roadmap to scale to 600mm × 600mm as equipment, materials, and yield mature. Fan-out chip-on-substrate and its bridge variant sit inside the VIPack™ advanced packaging platform as the organic-interposer path for chiplet integration — the complement to silicon-interposer 2.5D IC for designs that prioritize cost and package thickness. FOCoS eliminates the separate interposer entirely, supporting more than 1,000 I/O with lower insertion loss and lower warpage than a 2.5D build.

ASE is explicit that panel-level fan-out at this scale is not a solo effort. Achieving it depends on close collaboration with equipment makers, material suppliers, and automation partners — the same ecosystem model that VIPack™ and the Integrated Design Ecosystem™ (IDE) are built to coordinate.

What Comes Next

The demonstration of Fan-Out Chip Last on a 300mm panel — higher density, larger module sizes, and reliability parity with established wafer-level builds — gives AI and HPC customers a credible path to interposers beyond the reticle and beyond the wafer's economic limit. As panels scale toward 600mm and RDL layer counts climb to feed HBM4-class memory, the panel platform is positioned to absorb chiplet counts that the round wafer simply cannot host efficiently.

Evaluating a large-interposer chiplet design? Explore how ASE's FOCoS and panel-level fan-out solutions integrate ASIC and HBM at scale at ase.aseglobal.com.

Frequently Asked Questions

Q: What is the difference between FOWLP and FOPLP? A: Fan-out wafer-level packaging (FOWLP) builds fan-out packages on a round 300mm wafer, while fan-out panel-level packaging (FOPLP) builds them on a rectangular panel. The panel uses its area more completely — fitting 16 large interposers where a wafer fits 9 at 5.5x reticle size, a 1.78x efficiency gain — and improves material use, throughput, and warpage control for large interposers above 3x reticle size.

Q: What is Fan-Out Chip Last packaging? A: In the Chip Last approach, the redistribution layer (RDL) interposer is fabricated first on a carrier, and then known-good dies are attached to the finished interposer. This is the route used to integrate large ASICs with high bandwidth memory (HBM) because the RDL is completed before expensive dies are committed; these interposers exceed 1x reticle size and may require up to nine RDL layers with fine lines at 2μm/2μm L/S.

Q: Why use Laser Direct Imaging (LDI) for panel-level fan-out? A: An AI chiplet interposer is usually larger than a single lithography exposure field, which on a wafer scanner requires multi-reticle stitching. LDI is a maskless exposure method that patterns the full panel without stitching and compensates for panel distortion through software settings, making it well suited to the larger, square panel format.

Q: What did ASE's 300mm panel test vehicles demonstrate? A: Test Vehicle-1 integrated 10 chiplets (SoC-1 and SoC-2) with 10 silicon bridge dies and showed excellent adhesion with no delamination across all interlayers. Test Vehicle-2 integrated SoC-1 and SoC-2 dies with multiple-layer RDL and passed reliability tests, confirming exceptional interlayer quality.

Q: How does panel-level fan-out support AI and HPC packaging? A: AI and HPC accelerators place HBM stacks beside compute dies on a common interposer to raise bandwidth, which drives interposer sizes past 3x reticle and beyond. Panel-level fan-out delivers the larger module sizes, higher density, and better material efficiency these large interposers need, giving customers a scalable path as chiplet counts and HBM stacks increase.

✏️ AI 標題改寫建議

原始標題： Advanced Packaging from FOWLP to FOPLP Development of FanOut Chip Last in 300 mm Panel

建議標題： From Wafer to Panel: How ASE's 300mm FOPLP Chip-Last Process Fits 1.78x More AI Interposers with Zero Interlayer Delamination

改寫理由： 原始標題為學術論文式長句，資訊密但缺乏讀者利益與量化鉤子。建議標題以「wafer→panel」的核心轉變開場，前置最具說服力的兩個數據（1.78x 面積效率、零層間分層），並點明 AI interposer 應用情境，提升 SEO 點擊率與技術決策者的閱讀動機。依 skill 規則，Ghost 文章標題沿用原始標題，本建議僅供編輯團隊參考。

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