Shrinking a system-in-package (SiP) module to fit a smartwatch or a 5G RF front-end comes with a hidden penalty: a smaller footprint means a smaller solder joint area between the module and the printed circuit board (PCB), and that is exactly the connection that fails first when the device is dropped. ASE's finite element study of dual-side molding (DSM) SiP modules under JEDEC drop testing isolates two design levers that recover the lost reliability — increasing epoxy molding compound (EMC) coverage over the solder ball joints, and increasing solder joint volume. Both reduce the stress that drop impact concentrates in the outermost joints, giving designers a way to miniaturize without trading away ruggedness.
The challenge: miniaturization erodes drop reliability
SiP modules dominate portable electronics — Internet of Things (IoT) devices and mobile consumer equipment — precisely because they integrate many components in one package and shrink the board. Dual-side molding pushes that further: by assembling and molding components on both the top and bottom of the substrate, DSM achieves 20–40% smaller X-Y size than a single-side-molded package, along with a thinner profile and lower cost. That is why DSM has become the format of choice for RF front-end modules (FEM) — including the WiFi, mmWave FEM, and wearable (smartwatch, true wireless stereo) modules where every fraction of a millimeter counts.
The trade-off is mechanical. A smaller package shrinks the solder joint connection area to the PCB, and under the high-strain-rate loading of a drop event, that reduced area concentrates stress in the joints most exposed to board flexure. Left unaddressed, board-level drop reliability can be severely impaired — a serious risk for devices that, by definition, get dropped.
ASE's approach: validated simulation plus full-factorial DOE
Rather than qualify by trial and error, ASE built a numerical model of a DSM SiP package undergoing a drop impact test performed in accordance with the Joint Electron Device Engineering Council (JEDEC) standard. The model was then combined with a full-factorial design-of-experiments (DOE) method, which systematically varies the main design parameters of the DSM SiP package to quantify how each one affects solder joint reliability — rather than changing one variable at a time and missing interactions between them.
| Study element | Specification |
|---|---|
| Package type | Dual-side molding (DSM) SiP module |
| Test standard | JEDEC board-level drop impact |
| Method | Numerical (finite element) model + full-factorial DOE |
| Design parameters studied | EMC coverage of solder ball joints, solder joint volume, and other package parameters |
| Critical failure site | Outermost solder joints under board flexure |
This approach turns a pass/fail drop test into a parametric map: instead of learning only whether a given build survives, the team learns which parameters move reliability and by how much, in what direction.
Results: two levers that recover drop reliability
The study identified two design choices that meaningfully improve solder joint reliability under drop loading.
| Design lever | Effect on drop reliability | Mechanism |
|---|---|---|
| Higher EMC coverage of solder ball joints | Significant improvement | EMC encapsulation stiffens and protects the joint, reducing the strain it absorbs during board flexure |
| Larger solder joint volume | Improvement | A larger joint absorbs a greater share of the impact load and energy, lowering peak stress |
A higher EMC coverage of the solder ball joints yields a significant improvement in solder joint reliability: encapsulating more of the joint with molding compound constrains its deformation and shields it from the worst of the board-level strain during impact. Separately, a larger solder joint volume is beneficial because the bigger joint absorbs a greater proportion of the impact load and energy, reducing the stress that would otherwise be concentrated in a small contact area.
For a packaging engineer, these are directly actionable. If a wearable or RF module is failing board-level drop qualification, the study points to two concrete moves — extend EMC coverage over the perimeter solder joints, and size up the joint volume at the critical edge locations — before resorting to a larger, costlier footprint. Because the findings come from a JEDEC-aligned, validated model rather than a single build, they generalize across DSM SiP designs.
Where this fits in ASE's SiP and co-design portfolio
Dual-side molding is part of ASE's broader SiP offering, which spans BGA and LGA (ENIG and pre-solder) constructions at I/O pitches down to 0.35 mm for BGA and 0.28 mm for LGA, with optional compartment shielding for EMI-sensitive RF chipsets. Reliability work like this drop study is the engineering substrate beneath that portfolio: it feeds ASE's co-design and Integrated Design Ecosystem™ flow, where mechanical reliability constraints can be evaluated against electrical and form-factor targets early, so a module is designed to pass JEDEC drop the first time rather than after a respin.
The road ahead
As wearables and RF front-end modules continue to shrink while integrating more components, board-level mechanical reliability will only grow in importance relative to electrical performance. The parametric, JEDEC-validated methodology demonstrated here gives ASE and its customers a repeatable way to balance miniaturization against ruggedness — and to set EMC coverage and solder joint volume deliberately rather than by default.
Design a rugged, miniaturized SiP with ASE
If you are integrating an RF front-end or wearable module and need it to survive board-level drop without growing the footprint, ASE's dual-side molding and SiP design expertise can help you tune EMC coverage and joint geometry from the start. Explore ASE's system-in-package and double-side molding solutions at ase.aseglobal.com.
Frequently Asked Questions
Q: What is dual-side molding (DSM) in SiP packaging? A: Dual-side molding assembles and molds components on both the top and bottom sides of the substrate. This enables 20–40% smaller X-Y size than a single-side-molded package, a thinner profile, and lower cost, making it well suited to RF front-end modules and wearable devices where space is tightly constrained.
Q: Why does miniaturization hurt board-level drop reliability? A: A smaller package reduces the solder joint connection area between the SiP module and the PCB. During a drop event, the board flexes and concentrates stress in that reduced contact area — especially in the outermost joints — which can severely impair board-level drop reliability if not addressed in design.
Q: How can EMC coverage improve solder joint drop reliability? A: ASE's study found that higher epoxy molding compound (EMC) coverage of the solder ball joints yields a significant improvement in reliability. Encapsulating more of the joint constrains its deformation and shields it from board-level strain during impact, reducing the stress the joint must absorb.
Q: Does a larger solder joint volume help in drop testing? A: Yes. A larger solder joint volume absorbs a greater proportion of the impact load and energy produced in a drop event, lowering the peak stress concentrated in the joint. It is one of the two main design levers the study identified for improving drop reliability.
Q: How did ASE evaluate DSM SiP drop reliability? A: ASE built a finite element numerical model of a DSM SiP package subjected to a JEDEC-standard board-level drop impact test, then combined it with a full-factorial design-of-experiments method to quantify how each major design parameter affects solder joint reliability — capturing parameter interactions rather than testing one variable at a time.
Published in: IEEE Transactions on Electron Devices (Volume 70, Issue 1, January 2023).
✏️ AI 標題改寫建議
原始標題： Board-Level Drop Impact Reliability Analysis of Dual-Side Molding System-in-Package (SiP) Modules
建議標題： Two Design Levers That Save Drop Reliability in Miniaturized DSM SiP Modules — EMC Coverage and Solder Joint Volume
改寫理由： 原始標題完整但偏學術描述，未傳達讀者能帶走的具體結論。建議標題前置最具行動力的發現（兩個設計槓桿：EMC coverage 與 solder joint volume），明確點出讀者利益（在微縮下挽救 drop reliability），提升 SEO 與封裝工程師的閱讀動機。
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原始文章 Original → : Board-Level Drop Impact Reliability Analysis of Dual-Side Molding System-in-Package (SiP) Modules
