Thermal and Mechanical Characterization of 2.5D and Fan-Out Chip on Substrate Chip-First and Chip-Last Packages

When designers partition an AI or HPC processor across multiple dies, the package stops being a passive carrier and becomes a structural system. Each die, redistribution layer (RDL), and solder interconnect expands at a different rate as the package swings from a 30 °C idle to a 260 °C reflow, and that coefficient of thermal expansion (CTE) mismatch is where warpage, cracked dielectrics, and failed solder joints originate. Before committing a multi-die design to one architecture, an engineer needs to know which of the leading heterogeneous integration (HI) options — 2.5D IC, Fan-Out Chip-on-Substrate (FOCoS) chip-first, or FOCoS chip-last — best contains those thermomechanical stresses. ASE addressed that question directly in a study published in IEEE Transactions on Components, Packaging and Manufacturing Technology (Vol. 12, Issue 2, February 2022).

Three Heterogeneous Integration Architectures, One Comparison Framework

Heterogeneous integration combines multiple separately manufactured dies into a single higher-level assembly with greater functionality than a monolithic chip can deliver. The study compares the three architectures ASE customers most often weigh for multi-die logic-and-memory designs.

Architecture	Interconnect approach	Where it fits
2.5D IC	Through silicon via (TSV) silicon interposer	Maximum die-to-die density, interposer-grade routing
FOCoS chip-first (FOCoS-CF)	RDL built directly around dies, no interposer	Logic-to-logic chiplet partitioning
FOCoS chip-last (FOCoS-CL)	Pre-built RDL plus copper micro-bumps	ASIC co-packaged with high bandwidth memory (HBM)

Both FOCoS variants build the RDL on a reconstituted fan-out wafer at line width/line spacing (L/S) as fine as 2μm/2μm, delivering interposer-class interconnect without the TSV interposer that defines 2.5D IC. That structural difference — silicon interposer versus fan-out RDL — is exactly what drives the contrasting thermomechanical behavior the study set out to quantify.

A 3-D Nonlinear Simulation Model, Validated Against Hardware

The team built a nonlinear three-dimensional finite-element model to predict four failure-relevant responses across all three packages: package warpage, extreme low-k (ELK) interconnect stress on the die, RDL trace stress, and board-level solder joint reliability. A simulation is only as trustworthy as its correlation to hardware, so the model was validated against measured data: the predicted in-plane dimensional change of a FOCoS chip-last package matched experimental observations across the full 30 °C to 260 °C range that spans operating and assembly conditions. With that correlation established, the model becomes a design tool rather than an academic exercise — ASE can screen structural choices in simulation before cutting silicon.

Warpage, Dielectric Stress, and Solder-Joint Reliability

The four responses are coupled, and the architecture choice shifts the balance among them. ELK dielectrics are brittle and fracture-prone, so the stress transmitted into the ELK stack during thermal cycling governs front-end-of-line integrity. RDL trace stress determines whether the fine-line copper routing survives repeated expansion and contraction. Package warpage sets the limits for board assembly yield, and board-level solder joint reliability decides field lifetime once the package is mounted. Because the silicon interposer in 2.5D, the encapsulant-dominated structure of FOCoS chip-first, and the micro-bump interface of FOCoS chip-last each redistribute strain differently, the study compares them on a common basis rather than asserting a single winner — giving designers the response data to match an architecture to whichever failure mode dominates their reliability budget. Specific stress and warpage magnitudes for each architecture are reported in the IEEE paper [TBD - 待確認].

Thermal Performance Across the Three Packages

The study also compares junction-to-ambient thermal resistance across the three packages — the metric that ties packaging structure to how hard the silicon can run before it throttles. For the multi-die AI and HPC workloads these architectures target, every degree of junction temperature headroom translates into sustained clock frequency, so thermal resistance is not a secondary concern but a first-order design constraint. The measured thermal resistance values for the 2.5D, FOCoS-CF, and FOCoS-CL test structures are detailed in the published paper [TBD - 待確認].

The Polyimide Insight: Where Design-of-Experiments Pays Off

The most actionable result comes from the reliability optimization. The team ran a 2⁵ factorial design of experiments with analysis of variance (ANOVA) to isolate which structural parameters most affect the thermomechanical reliability of the FOCoS chip-last package under typical thermal loading. The analysis identified the polyimide (PI) dielectric thickness as a controlling factor: a thinner PI layer improves package reliability by minimizing the CTE mismatch between the PI layer and the copper RDL trace. For a package designer, this is a direct lever — adjusting a dielectric thickness specification, rather than redesigning the die stack, measurably raises the reliability margin. Pinpointing that lever through ANOVA, rather than trial-and-error build-and-test cycles, is what compresses a reliability qualification from many silicon spins to a focused set of validated changes.

Why a Validated Model Changes the FOCoS Design Conversation

Taken together, the study turns a qualitative debate — "is fan-out reliable enough versus a silicon interposer?" — into a quantitative, model-backed selection process. A correlated simulation that predicts warpage, ELK stress, RDL stress, and solder-joint life lets ASE and its customers evaluate 2.5D, FOCoS-CF, and FOCoS-CL against each program's specific thermal envelope and reliability targets before tooling. That is the practical advantage of co-design: the architecture decision, the dielectric stack, and the assembly window are settled in simulation, shortening the path from concept to a qualified, manufacturable package.

FOCoS Within the VIPack™ Platform

FOCoS chip-first and chip-last are two of the fan-out pillars of ASE's VIPack™ advanced packaging platform, which spans Fan-Out Chip-on-Substrate (FOCoS), Fan-Out Chip-on-Substrate-Bridge (FOCoS-Bridge), Fan-Out Package-on-Package (FOPoP), Fan-Out System-in-Package (FOSiP), and TSV-based 2.5D/3D IC. Reliability characterization like this study feeds ASE's Integrated Design Ecosystem™ (IDE), where validated material and structural models let customers co-optimize signal integrity, thermal performance, and mechanical reliability across silicon, package, and board in a single flow.

Conclusion

As chiplet partitioning becomes standard for AI and HPC silicon, thermomechanical reliability is no longer a back-end checkbox — it is an architecture-level decision made at the start of a design. By building and hardware-validating a 3-D nonlinear model across 2.5D IC, FOCoS chip-first, and FOCoS chip-last, and by isolating the polyimide layer as a reliability lever through ANOVA, ASE gives designers a defensible, data-driven basis for choosing and tuning a heterogeneous integration package. As the world's largest outsourced semiconductor assembly and test (OSAT) provider, ASE pairs that characterization depth with volume manufacturing — so a reliability-optimized FOCoS design can move from simulation to production on one platform.

Explore FOCoS and the VIPack™ platform: Learn how ASE's fan-out and heterogeneous integration technologies can accelerate your next AI or HPC design at ase.aseglobal.com.

Frequently Asked Questions

Q: What is the difference between FOCoS chip-first and FOCoS chip-last packaging? A: In FOCoS chip-first (FOCoS-CF), the redistribution layer (RDL) is built directly around the dies after they are placed, connecting chiplets without micro-bumps at the RDL interface. In FOCoS chip-last (FOCoS-CL), the RDL is fabricated first and the dies — typically an ASIC alongside high bandwidth memory (HBM) — are attached afterward using copper micro-bumps. Both use fan-out RDL at line width/line spacing (L/S) as fine as 2μm/2μm instead of a silicon interposer.

Q: How do 2.5D IC and FOCoS packages differ in thermomechanical reliability? A: 2.5D IC uses a through silicon via (TSV) silicon interposer, while FOCoS builds its interconnect on a reconstituted fan-out wafer with no interposer. Because the silicon interposer, the encapsulant in FOCoS chip-first, and the micro-bump interface in FOCoS chip-last each redistribute thermal strain differently, they show different warpage, dielectric stress, and solder-joint reliability behavior — which is why ASE characterized all three with a common validated model.

Q: Why does polyimide layer thickness affect package reliability? A: The polyimide (PI) dielectric and the copper RDL trace have different coefficients of thermal expansion (CTE). As temperature cycles, that mismatch induces stress in the RDL. ASE's design-of-experiments study found that a thinner PI layer minimizes this CTE mismatch, improving the thermomechanical reliability of the FOCoS chip-last package.

Q: How did ASE validate its package simulation model? A: ASE built a 3-D nonlinear finite-element model and confirmed its accuracy by comparing the predicted in-plane dimensional change of a FOCoS chip-last package against experimental measurements across the 30 °C to 260 °C temperature range. The correlation between simulation and hardware makes the model usable for predictive design screening.

Q: What is extreme low-k (ELK) interconnect stress and why does it matter? A: Extreme low-k dielectrics are used in advanced silicon back-end-of-line layers to reduce signal delay, but they are mechanically brittle. The stress transmitted into the ELK stack during thermal cycling can crack these layers, so quantifying ELK interconnect stress is essential to ensuring the die survives inside a heterogeneous integration package.

✏️ AI 標題改寫建議

原始標題： Thermal and Mechanical Characterization of 2.5D and Fan-Out Chip on Substrate Chip-First and Chip-Last Packages

建議標題： 2.5D vs FOCoS Chip-First vs Chip-Last: A Validated Model for Warpage, Stress, and Solder-Joint Reliability

改寫理由： 原始標題為標準學術論文格式，技術完整但缺乏對比張力與讀者利益。建議標題以三種架構直接對比（vs）開場，前置讀者最關心的可靠度指標（warpage、stress、solder-joint reliability），並點出「validated model」的可信度，符合七大規則中的「具體問題前置」與「讀者利益前置」，提升 SEO 點擊率與封裝工程師的閱讀動機。

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